Many clock multiplexers produce glitches under some conditions when switching from one clock source to another clock source. Some clock multiplexing schemes place restrictions on the switch control events and/or on the clock signals being switched. An example is U.S. Pat. No. 6,075,392 which assumes that the switch control events are synchronous to the currently selected clock signal and also assumes that the currently selected clock signal is active and transitioning. If the currently selected clock signal begins to start transitioning erratically or fails entirely such that it is no longer transitioning, then the clock multiplexing scheme may not be able to transition from the currently selected clock signal to another clock signal in a glitch-free manner.